1. Field of the Invention
The invention generally relates to computer bus systems and in particular to a method and apparatus for controlling edge rates of signals driven onto a computer bus herein referred to as a transmission line.
2. Description of Related Art
To achieve the fastest possible bus transmission rates within modern computer systems it is necessary to provide the fastest possible switching rates between logic low and logic high signals while also minimizing noise and other factors which can affect the ability to detect signals. As far as switching rates are concerned, it is desirable to provide the fastest possible edge rate. By edge rate, it is meant the rate at which the voltage level of the bus signal is pulled up from a logic low voltage level to a high voltage level or vice versa. Depending upon the implementation, an edge rate of about 1 volt per nanosecond is desirable. However, the faster the switching rate, the more likely ringing and other noise affects will result. Indeed, a sharp transition from either a high to a low or from a low to a high signal level will result in substantial ringing requiring a considerable settling time. Settling time limits the ability to reliably detect the signal level, thereby limiting how quickly successive transitions can be asserted which in turn limits the data transfer rate. In many systems the fastest overall transmission rates are achieved with a tradeoff between fast edge rate transitions and overall system noise.
One technique for achieving an adequate compromise between fast edge rates and low noise is to provide a phased output driver for driving the bus transmission line wherein several separate output transistors are sequentially activated, perhaps over a period of one or two nanoseconds, to achieve a fairly smooth transition between low and high signal states. Hence, whereas a single output transistor may be capable of achieving the fastest possible signal transition, the system noise as a result of the resulting sharp transition prevents an overall high data transmission rate. By providing several output transistors which are sequentially triggered, the slope of the rising or falling edge of the signal is smoothed out to minimize ringing and other noise caused by a sharp transition while still achieving a relatively fast overall signal transition.
An example of a phased output driver is illustrated in FIG. 1. The phased output driver of FIG. 1 is employed within a bus system using Gunning Transceiver Logic (GTL) wherein individual drivers pull down the signal level on the bus. A passive pull up resistor, not illustrated in FIG. 1, is provided on the bus transmission line for pulling up the signal level once the line has been released by the phased output drive.
More specifically, FIG. 1 illustrates a GTL phased output driver 10 having a NOR-gate pre-driver 12, a set of phasing or delay elements 14 and a set of output transistors 16. NOR-gate pre-driver 12 is connected to input and enable# lines 18 and 20, respectively. A single output of NOR-gate 12 is connected into the first of a pair of pass gate phasing elements 14. The pair of phasing elements are denoted by reference numerals 22 and 24. A signal output by NOR-gate 12 is delayed first by pass gate 22, then again by pass gate 24. The set of output transistors includes three individual transistors, denoted 26, 28 and 30 which are connected to differing locations along the delay line of phasing elements. In particular, a gate of transistor 26 is connected directly into the output of NOR-gate 12. A gate of transistor 28 is connected into the output of pass gate 22. Finally a gate of transistor 30 is connected into an output of pass gate 24. Drains of each of the three output transistors are connected to an output line 32.
With this configuration, during a pull down phase output transistor 26 is triggered first, then, after a time delay provided by pass gate 22, transistor 28 is triggered. Finally, after a second time delay provided by pass gate 24, output transistor 30 is triggered. In this manner, the three output transistors are sequentially triggered-to generate an output signal which is pulled down from a high voltage to a low voltage at an overall rate which depends upon the switching strengths of the individual transistors and upon the delay times of pass gates 22 and 24.
A low to high signal transition is achieved by sequentially deactivating the output transistors to provide a controlled release of the output line allowing the external passive resistor (not shown) to pull up the line. The output transistors are released in the same order in which they are activated during a pull down.
FIG. 2 illustrates an idealized high to low signal transition 34 as well as a high to low transition 36 generated by the phased output driver of FIG. 1. As can be seen, signal 36 provides a smooth and relatively noise free transition from a high voltage level to a low voltage level over a period of several nanoseconds. FIG. 2 also illustrates points in time 38, 40 and 42 when the separate output transistors 26, 28 and 30, respectively, of FIG. 1, are triggered. As can be seen, a time delay, caused by the pass gate elements, occurs between the respective triggering times. The relatively fast smooth signal transition illustrated in FIG. 2 is achieved for a high to low signal transition by ensuring that transistor 30 (FIG. 2) is much stronger than transistors 26 and 28. Transistor 30 must be much stronger than the other two transistors because it is triggered last and therefore must pull down the voltage from a level which is already rather low. However, when the same circuit releases the output line, thereby allowing the passive transistor to pull up the line, the resulting low to high transition is neither as fast nor as smooth.
FIG. 3 illustrates an idealized low to high transition 44 and a transition 46 generated by the phased output driver of FIG. 1. Release times for the three transistors are also shown in FIG. 3. More specifically, points 48, 50 and 52 illustrate the release times of transistors 30, 28 and 26, respectively, of FIG. 1. As can be seen, the signal rises relatively slowly after the release of transistors 26 and 28, then jumps up erratically after transistor 30 is released, resulting in a substantial period of ringing which results in substantial system noise. The erratic noise occurs because transistor 30, which is triggered at time 52, is much stronger than the other two transistors. The system noise prevents prompt and reliable detection of the low to high transition by other elements connected to the bus and also prevents any prompt high to low transition.
As noted, to achieve the relatively fast transition of FIG. 2, transistor 30 must be much stronger than the other two transistors. When the transistors are operating to pull up the output signal, transistor 30, being quite strong, causes the abrupt and erratic signal transition illustrated in FIG. 3. The relative sizes of transistors could alternatively be tuned to provide for a smooth and quick low to high transition during the pull up phase, but such would result in an erratic jump in the high to low transition during the pull down phase. In known prior art systems, the sizes of transistors and the delays provided by the phasing elements are set to be equal such that adequate, but not exceptional, performance is achieved for both low to high and high to low transitions. As such, optimal data transmission rates are not achieved.
It would be desirable to provide an improved phased output driver for use with busses, particularly GTL-based busses, which achieves fast edge rates for both high to low and low to high transitions and also achieves minimal system noise levels. It is to that end that aspects of the invention are drawn.